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Three-dimensional integrated circuit
In microelectronics, a “three dimensional integrated circuit” (3D IC) is an integrated circuit manufactured by stacking silicon wafers and/or dies and interconnecting them vertically using through-silicon vias (TSVs) so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. 3D IC is just one of a host of 3D integration schemes that exploit the z-direction to achieve electrical performance benefits. They can be classified by their level of interconnect hierarchy at the global (package), intermediate (bond pad) and local (transistor) level 〔http://www.semi.org/cms/groups/public/documents/web_content/ctr_033139.pdf〕 In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs), monolithic 3D ICs; 3D heterogeneous integration; and 3D systems integration.〔http://www.3dincites.com/3d-incites-knowledge-portal/what-is-3d-integration/〕 International organizations such as the (Jisso Technology Roadmap Committee ) (JIC) and the International Technology Roadmap for Semiconductors (ITRS) have worked to classify the various 3D integration technologies to further the establishment of standards and roadmaps of 3D integration.〔http://www.itrs.net/Links/2011itrs/2011Chapters/2011Design.pdf〕
== 3D ICs vs. 3D packaging ==
3D Packaging refers to 3D integration schemes that rely on traditional methods of interconnect such as wire bonding and flip chip to achieve vertical stacks. 3D packaging can be disseminated further into 3D system in package (3D SiP) and 3D wafer level package (3D WLP). Stacked memory die interconnected with wire bonds, and package on package (PoP) configurations interconnected with either wire bonds, or flip chips are 3D SiPs that have been in mainstream manufacturing for some time and have a well established infrastructure. PoP is used for vertically integrating disparate technologies such as 3D WLP uses wafer level processes such as redistribution layers (RDL) and wafer bumping processes to form interconnects.
2.5D interposer is also a 3D WLP that interconnects die side-side on a silicon, glass or organic interposer using TSVs and RDL. In all types of 3D Packaging, chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board.
3D ICs can be divided into 3D Stacked ICs (3D SIC), which refers to stacking IC chips using TSV interconnects, and monolithic 3D ICs, which use fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the ITRS, this results in direct vertical interconnects between device layers. The first examples of a monolithic approach are seen in (Samsung’s 3D VNAND devices ).
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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